1. Field of the Invention
This invention relates to computing systems, and more particularly, to interleaving memory requests across memory channels.
2. Description of the Relevant Art
A computing system may issue memory requests through an interface to any of a plurality of memory channels. In some embodiments, addresses are interleaved among the memory channels to improve bandwidth utilization. Typically, a system address is interleaved by mapping the system address through a single range register and using modulo N arithmetic. Normally, interleaving is done across a power-of-two (i.e., 2n) number of channels. As an example, when memory is interleaved across four channels, any two address bits may be used to distribute the address space. The address bits used for interleaving are then dropped before the request is sent to a respective memory controller.
The techniques currently used to interleave an address space across non-power-of-two numbers of channels have a variety of shortcomings. For example, for a system with three memory channels, a common technique involves picking three address bits and distributing these address bits using mod 3 arithmetic. However, this will end up with two of the memory channels receiving three addresses and one memory channel receiving two. Therefore, there is a desire to support interleaving across memory channels including three channels or across other non-power-of-two numbers of channels.